• 22 Posts
  • 220 Comments
Joined 1 year ago
cake
Cake day: July 8th, 2023

help-circle































  • probably ur battery already formed dendrites, causing it to have micro shorts internally and thus spreading heat in the phone case. a phone with 10w charging causes the battery to heat, let alone ur galaxy s20 charging at 15w. i actively cool my phone battery while charging by putting it in front of a fan so the battery stays cool and doesn’t form dendrites, and thus stays healthy. i also use a silicon case instead of leather else u ll be thermally suffocating ur phone: it uses metal as a case material for a reason. exynos for s20 seem to be made on the 7nm process node which usually should be efficient in term of temps. even when the cpu heats up (even using the 4g antenna, let alone a 5g one when active, the camera flash, all those heats up and causes the phone case to heat up too and then a chain cycle ensues by causing the battery to heat up sponatneously too, then it dries up faster than usual which compels the user to plug the charger and the infinite cycle of heat will never end…i never owned an exynos phone but sometimes a phone need to be underpowered so it could last.samsung phones are really overperforming but unluckely their users aren’t just thermal conscious. no engineering degree is needed to have a grasp over phone thermals but sometimes having some knowledge is needed if u cherich ur phone




  • Intel unveiled its first direct mesh-to-mesh photonic fabric at the Hot Chips 2023 chip conference, highlighting its progress towards a future of optical chip-to-chip interconnects that are also championed by the likes of Nvidia and Ayar Labs. However, the eight-core 528-thread chip that Intel used for the demonstration stole the spotlight due to its unique architecture that sports 66 threads per core to enable up to 1TBs of data throughput. Surprisingly, the chip consumes only 75W of power, with 60 of the power being used by the optical interconnects, but the design could eventually enable systems with two million cores to be directly connected with under 400ns latency. Intels PUMA Programmable Unified Memory Architecture chip is part of the DARPA HIVE program that focuses on improving performance in petabyte-scale graph analytics work to unlock a 1000X improvement in performance-per-watt in hyper-sparse workloads. Surprisingly for an x86-centric company like Intel, the test chip utilizes a custom RISC architecture for streamlined performance in graph analytics workloads, delivering an 8X improvement in single-threaded performance. The chip is also created using TSMCs 7nm process, not Intels own internal nodes. After characterizing the target workloads, Intel concluded that it needed to craft an architecture that solved the challenges associated with extreme stress on the memory subsystem, deep pipelines, branch predictors, and out-of-order logic created by the workload. Intels custom core employs extreme parallelism to the tune of 66 hardware threads for each of the eight cores, large L1 instruction and data caches, and 4MB of scratchpad SRAM per core. The eight-core chip features 32 optical IO ports that operate at 32 GBsdir apiece, thus totaling 1TBs of total bandwidth. The chips drop into an eight-socket OCP server sled, offering up to 16 TBs of total optical throughput for the system, and each chip is fed by 32GB of custom DDR5-4000 DRAM. Intel fabbed the chip on TSMCs 7nm process with 27. 6 billion transistors spanning a 316mm2 die. The eight cores, which consume 1. 2 billion transistors, run down the center of the die, flanked by eight custom memory controllers with an 8-byte access granularity.